Communications transceivers may utilize numerous architectures to recover data from a modulated carrier signal. These architectures include coherent demodulation, using either intermediate frequency conversion or direct-conversion receivers. Such receivers typically recover or regenerate the communications carrier signal using a phase-locked loop (PLL) and coherent demodulation. Recently, polar receiver architectures have been proposed that extract the modulation phase components from a received modulated signal without using a carrier recovery circuitry. However, the proposed polar receiver architectures and associated signal processing have deficiencies that result in poor performance and high bit error rates (BER). Accordingly, there is a need for improved polar receiver signal processing and architectures.
Various signal processing architectures often make use of peak detectors to measure the peak level of a radio frequency signal. However, such detectors frequently require the use of a relatively high signal input level. For example, the amplitude detector disclosed by C. Zhang, R. Gharpurey, and J. A. Abraham, “Built-In Test of RF Mixers Using RF Amplitude Detectors,” IEEE ISQUED, 2007, requires an input signal amplitude of at least around 100 mV. For wireless receiver applications, a signal of that level can often be achieved only with the use of an additional amplifier to amplify the input of the peak detector. However, the use of an amplifier can lead to undesirably high levels of power consumption.